The present invention relates to a logic circuit, particularly to the art effectively applied to a high speed logic circuit to be formed within a semiconductor integrated circuit, namely to the art effectively applied, for example, to NTL (Non-Threshold Logic), or ECL (Emitter Coupled Logic) and, moreover, to the art effectively applied to the basic logic circuit within a bipolar gate array integrated circuit (for example, refer to Nikkei Electronics, No. 420, pp. 117-120, May 4, 1987, Nikkei McGraw-Hill, Inc.).
The present invention also relates to a technique effective for use in an NTL or ECL circuit provided with an active pull-down circuit.
Some NTL and ECL circuits proposed receive low amplitude digital input signals and conduct high speed logic operations. Moreover, an NTL circuit has been proposed with an output emitter follower and an ECL circuit with an emitter follower formed by adding the output emitter follower circuit to an NTL circuit and an ECL circuit (hereinafter, the NTL circuit with an output emitter follower is called an NTL circuit and the ECL circuit with an output emitter follower is called an ECL circuit, respectively), a high speed logic integrated circuit comprising the basic configuration of the NTL circuit and the high speed logic circuit comprising the basic configuration of an ECL circuit and an NTL circuit.
FIG. 32 is a configuration example of the logic circuit of prior art.
The logic circuit LOG.sub.7 shown in the same figure is formed as an NTL comprising a first transistor Q.sub.36 forming a grounded emitter type phase inversion circuit and a second transistor Q.sub.37 forming an emitter follower output circuit, and a negative logic output V.sub.010 can be obtained for an input V.sub.i7 as shown in FIG. 33 by applying an inversion output extracted from the collector of transistor Q.sub.36 to the base of transistor Q.sub.37.
In this case, this logic circuit LOG.sub.7 is provided with a collector load resistance R.sub.34, an emitter bias resistance R.sub.35, a speedup capacitance C.sub.a8 for improving switching operation of transistor Q.sub.36 and an emitter load resistance R.sub.36 of transistor Q.sub.37.
The NTL circuit is described, for example, in Japanese Patent Laid-Open No. 63-124615.